1. Field of the Invention
This invention relates to a semiconductor memory device including a variable resistance film and a method for manufacturing the same.
2. Background Art
Various nonvolatile memories including flash memory, MRAM (Magneto resistive Random Access Memory), and FeRAM (Ferroelectric Random Access Memory) are developed to realize nonvolatile memories with high speed and high capacity. In this context, it has recently been discovered that a specific metal oxide material upon application of voltage exhibits two states, i.e., a low-resistance state and a high-resistance state, depending on the state and the voltage at the time. This phenomenon is used to propose the idea of a new nonvolatile memory, ReRAM (Resistance Random Access Memory), which is drawing attention.
As a device structure for actually commercializing ReRAM, in order to increase the level of integration of memory cells, a three-dimensional cross-point structure is proposed, in which interconnect layers each including a plurality of word lines parallel to each other and interconnect layers each including a plurality of bit lines parallel to each other are alternately stacked on a peripheral circuit for operating memory cells, each being connected between one word line and one bit line (see, e.g., JP-T-2005-522045).
In the ReRAM of the three-dimensional cross-point structure, by selecting one word line and one bit line to selectively apply a voltage to one memory cell connected therebetween, the resistance state of a variable resistance element provided in the memory cell is controlled to program data. By applying a prescribed voltage to each memory cell and measuring the amount of current flowing therethrough, the resistance state of the variable resistance element is detected to read the programmed data.
In this case, in the program operation, for example, by applying a potential of +5 V to one selected bit line and a potential of 0 V to one selected word line, a voltage of +5 V is applied to the memory cell connected therebetween. Here, to avoid applying voltage to the memory cell between the selected bit line and a non-selected word line and the memory cell between the selected word line and a non-selected bit line, a potential of 0 V is applied to non-selected bit lines like the selected word line, and a potential of +5 V is applied to non-selected word lines like the selected bit line. However, this unfortunately results in applying a voltage of −5 V to the memory cell connected between a non-selected bit line and a non-selected word line.
To solve this problem, each memory cell is provided with a diode having the forward direction from the bit line to the word line. Thus, in the selected memory cell, a forward voltage is applied to the diode, and a voltage is applied to the variable resistance element. In contrast, in a non-selected memory cell connected between a non-selected word line and a non-selected bit line, a reverse voltage is applied to the diode, and no voltage is applied to the variable resistance element.
However, by providing the diode in the memory cell, the low forward current through the diode results in a small difference in the amount of current flowing in the high-resistance state of the variable resistance element and the amount of current flowing in the low-resistance state thereof, which causes the problem of narrowing the margin of read operation.